Micron Technology DRAM , Part #: MT49H16M36SJ-25E:B features: • 533 MHz DDR operation (1.067 Gb/s/pin data rate) • 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) • Organization – 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36 • 8 internal banks for concurrent operation and maximum bandwidth • Reduced cycle time (15ns at 533 MHz) • Nonmultiplexed addresses (address multiplexing option available) • SRAM-type interface • Programmable READ latency (RL), row cycle time, and burst sequence length • Balanced READ and WRITE latencies in order to optimize data bus utilization • Data mask for WRITE commands • Differential input clocks (CK, CK#) • Differential input data clocks (DKx, DKx#) • On-die DLL generates CK edge-aligned data and output data clock signals • Data valid signal (QVLD) • 32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms) • HSTL I/O (1.5V or 1.8V nominal) • 25–60Ω matched impedance outputs • 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O • On-die termination (ODT) RTT

MIL:MT49H16M36SJ-25E B

MT49H16M36SJ-25E:B